The present invention relates to semiconductor test equipment for testing characteristics of semiconductor memories, in particular, the operating power source current for each specified address of a semiconductor memory such as a CMOS memory.
In the testing of semiconductor memories, a test pattern and an expected value pattern are generated from a test pattern generator, the test pattern is applied to the memory under test and data available therefrom is compared with the expected value pattern, thereby deciding whether the memory under test is non-defective or defective.
It is well known that a CMOS memory, for example, is very small in power consumption. Accordingly, the CMOS memory is often used in the battery-driven mode. When the semiconductor is used in such a battery-driven mode, it is important how many hours the semiconductor memory can be operated from the battery. Therefore, it is required that power dissipation of the semiconductor memory will not exceed a predetermined value, and it is tested whether the power dissipation will exceed the predetermined value or not.
That is, in the case of testing characteristics of semiconductor memories of low power consumption, such as the CMOS memory and so on, it is necessary to make a test of their operating power source current so as to measure their power dissipation, in addition to an ordinary logic test, a DC test, etc. The operating power source current which flows into the semiconductor usually differs in value with addresses assigned thereto. Therefore, in conventional testing of such a power source current it is customary to decide an address of the memory under test to which particular attention is to be paid and to measure the current value at that address, or to measure the power source current at all addresses of the memory under test, examining at which address the operating power source current exceeds a predetermined value.
FIG. 1 illustrates in block form the arrangement of a conventional semiconductor memory tester of this kind. In FIG. 1, a test pattern generator 101 generates a test pattern 105 and an expected value pattern 107 in synchronism with a clock signal 103 from a timing generator 102. The test pattern 105 is composed of an address data, write data and control data for input into a memory under test 112. The test pattern 105 is applied to a waveform shaper 106, wherein it is shaped into a desired waveform, thereafter being provided therefrom to the memory under test 112. The expected value pattern 107 is supplied to a logic comparator 108, wherein it is logic-compared with the output signal from the memory under test 112. For example, as shown in FIG. 2 of U.S. Pat. No. 4,293,950 issued on Oct. 6, 1981, the test pattern and the expected value pattern are generated by executing a program transferred in advance from a central control unit 104 to the test pattern generator 101 via a bus line 119.
The timing generator 102 generates the clock signal 103 for the test pattern generator 101, a clock signal 110 for the waveform shaper 106 and a strobe signal 111 for determining the timing for comparison in the logic comparator 108, in accordance with periods and phases transferred in advance from the central control unit 104 to the timing generator 102 via the bus line 109 when a signal 109, which is applied thereto from the test pattern generator 101, is at the logic "0".
The waveform shaper 106 shapes the waveform of the test pattern 105 from the test pattern generator 101 into a test pattern 113 of a waveform, timing and an amplitude predetermined by the central control unit 104 via the bus line 119, and provides the pattern 113 to the memory under test 112. The logic comparator 108 makes a logic comparison between data 114 output from the memory under test 112 as a result of the application thereto of the test pattern 113 and the expected value pattern 107 from the test pattern 101, and the logic comparator 108 provides the comparison result 115 to the test pattern generator 101. When the comparison result 115 indicates noncoincidence between the output of the memory under test 112 and the expected value pattern 107, for instance, the signal 109 from the test pattern generator 101 is changed to logic "1" to halt the operation of the timing generator 102 and the memory under test 112 is removed as defective. Alternatively, the operation stop function may be set nonoperative and the comparison result 115 may be stored in a "defective" address memory (not shown) which is specified by the address of the test pattern 113 at that time.
In this way, the memory under test 112 is subjected to the logic test. In the test of such a semiconductor memory, it may sometimes necessary to measure the power source current flowing in the memory under test. This measurement is carried out in such a manner as follows: A power source circuit 116 generates a voltage predetermined by the central control unit 104 via the bus line 119 in accordance with the type of the memory under test 112, and provides the voltage via a current measuring circuit 118 to an operating power source terminal 121 of the memory under test 112. The current measuring circuit 118 measures the value of a current 117 which flows into the memory under test 112 from the power source circuit 116, and transfers the measured result as a digital value to the central control unit 104 via the bus line 119. The central control unit 104 decides whether the measured result is below a predetermined value or not, and then advances the test pattern to the next cycle.
That is, with such a conventional power source current measuring method, a series of test patterns for the memory under test 112 are caused to advance cycle by cycle under control of the central control unit 104 and when the address of the memory under test 112 to which the power source current is applied has reached the specified address to which particular attention is to be paid for measurement of the power source current, the central control unit 104 decides the measured result from the current measuring circuit 118. When the measured result is below a predetermined value, the central control unit 104 commands the test pattern generator 101 to proceed to the next cycle. If the measured current value is above the predetermined value, the memory under test 112 is decided as defective.
With such a conventional semiconductor memory test equipment, in the case of measuring the power source current of the memory under test, the central control unit 104 decides the measured value of the power source current for each cycle of the test pattern and then instructs the test pattern generator 101 to proceed to the next cycle, thus going ahead with the test. On account of this, the period of each cycle of the test pattern is lengthened, resulting in the defect of the test becoming time-consuming.
As described above, in the case of testing the power source current of the memory under test by the conventional semiconductor memory test equipment, the time for testing becomes long and this is marked especially in the case of testing large-capacity semiconductor memories. Therefore, the efficiency of testing has been low and the cost for testing has led to an appreciable increase in the manufacturing costs of semiconductor memories.